1. Field of the Invention
The present invention generally relates to a thin film magnetic memory device. More particularly, the present invention relates to a thin film magnetic memory device capable of random access and including memory cells having a magnetic tunnel junction (MTJ).
2. Description of the Background Art
An MRAM Magnetic Random Access Memory) device has attracted attention as a memory device capable of non-volatile data storage with low power consumption. The MRAM device is a memory device capable of non-volatile data storage using a plurality of thin film magnetic elements formed in a semiconductor integrated circuit and also capable of random access to each thin film magnetic element.
In particular, recent announcement shows that the performance of the MRAM device is significantly improved by using tunnel magnetic resistive elements having a magnetic tunnel junction (MTJ) as memory cells. The MRAM device including memory cells having a magnetic tunnel junction is disclosed in technical documents such as “A 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in Each Cell”, ISSCC Digest of Technical Papers, TA7.2, February 2000, and “Nonvolatile RAM based on Magnetic Tunnel Junction Elements”, ISSCC Digest of Technical Papers, TA7.3, February 2000.
FIG. 13 is a schematic diagram showing the structure of a memory cell having a magnetic tunnel junction (hereinafter, sometimes simply referred to as “MTJ memory cell”).
Referring to FIG. 13, the MTJ memory cell includes a tunnel magnetic resistive element TMR having its electric resistance value varying according to the storage data level, and an access transistor ATR. The access transistor ATR is formed from a field effect transistor, and is coupled between the tunnel magnetic resistive element TMR and the ground voltage VSS.
For the MTJ memory cell are provided a write word line WWL for instructing a data write operation, a read word line RWL for instructing a data read operation, and a bit line BL serving as a data line for transmitting an electric signal corresponding to the storage data level in the data read and write operations.
FIG. 14 is a conceptual diagram illustrating the data read operation from the MTJ memory cell.
Referring to FIG. 14, the tunnel magnetic resistive element TMR has a magnetic layer FL having a fixed magnetic field of a fixed direction (hereinafter, sometimes simply referred to as “fixed magnetic layer FL”), and a magnetic layer VL having a free magnetic field (hereinafter, sometimes simply referred to as “free magnetic layer VL”). A tunnel barrier TB of an insulator film is provided between the fixed magnetic layer FL and the free magnetic layer VL. According to the storage data level, either a magnetic field of the same direction as that of the fixed magnetic layer FL or a magnetic field of the direction different from that of the fixed magnetic layer FL has been written to the free magnetic layer VL in a non-volatile manner.
In the data read operation, the access transistor ATR is turned ON in response to activation of the read word line RWL. As a result, a sense current Is flows through a current path formed from the bit line BL, tunnel magnetic resistive element TMR, access transistor ATR and ground voltage VSS. The sense current Is is supplied as a constant current from a not-shown control circuit.
The electric resistance value of the tunnel magnetic resistive element TMR varies according to the relative relation of the magnetic field direction between the fixed magnetic layer FL and the free magnetic layer VL. More specifically, when the fixed magnetic layer FL and the free magnetic layer VL have the same magnetic field direction, the tunnel magnetic resistive element TMR has a smaller electric resistance value as compared to the case where both magnetic layers have different magnetic field directions. The electric resistance values of the tunnel magnetic resistive element corresponding to the storage data “1” and “0” are herein indicated by R1 and R0, respectively (where R1>R0 and R1=R0+ΔR).
The electric resistance value of the tunnel magnetic resistive element TMR thus varies according to an externally applied magnetic field. This enables data storage to be conducted based on the variation characteristics of the electric resistance value of the tunnel magnetic resistive element TMR. In general, the tunnel magnetic resistive element TMR that is applied to the MRAM devices has an electric resistance value in the range from about several kilo-ohms to about several tens of kilo-ohms.
A voltage change In the tunnel magnetic resistive element TMR due to the sense current Is varies depending on the magnetic field direction stored In the free magnetic layer VL. Therefore, by starting supply of the sense current Is with the bit line BL precharged to a high voltage, the storage data level in the MTJ memory cell can be read by monitoring a change in voltage level on the bit line BL.
FIG. 15 is a conceptual diagram illustrating the data write operation to the MTJ memory cell.
Referring to FIG. 15, in the data write operation, the read word line RWL is inactivated, so that the access transistor ATR is turned OFF. In this state, a data write current for writing a magnetic field to the free magnetic layer VL is supplied to the write word line WWL and the bit line BL. The magnetic field direction of the free magnetic layer VL is determined by combination of the respective directions of the data write currents flowing through the write word line WWL and the bit line BL.
FIG. 16 is a conceptual diagram illustrating the relation between the respective directions of the data write current and the magnetic field in the data write operation.
Referring to FIG. 16, a magnetic field Hx of the abscissa indicates the direction of a magnetic field H(BL) produced by the data write current flowing through the bit line BL. A magnetic field Hy of the ordinate indicates the direction of a magnetic field H(WWL) produced by the data write current flowing through the write word line WWL.
The magnetic field direction stored in the free magnetic layer VL is updated only when the sum of the magnetic fields H(BL) and H(WWL) reaches the region outside the asteroid characteristic line shown in the figure. In other words, the magnetic field direction stored in the free magnetic layer VL is not updated when a magnetic field corresponding to the region inside the asteroid characteristic line is applied.
Accordingly, in order to update the storage data of the tunnel magnetic resistive element TMR by the data write operation, a current must be applied to both the write word line WWL and bit line BL. Once stored in the tunnel magnetic resistive element TMR, the magnetic field direction, i.e., the storage data, is retained therein in a non-volatile manner until another data write operation is conducted.
The sense current Is flows through the bit line BL in the data read operation. However, the sense current Is is generally set to a value that is about one to two orders smaller than the data write current. Therefore, it is less likely that the storage data in the MTJ memory cell is erroneously rewritten by the sense current Is during the data read operation.
The aforementioned technical documents disclose the technology of forming an MRAM device, a random access memory, by integrating such MTJ memory cells on a semiconductor substrate.
FIG. 17 is a conceptual diagram showing the MTJ memory cells arranged in a matrix in an integrated manner.
Referring to FIG. 17, a highly integrated MRAM device can be realized by arranging the MTJ memory cells in a matrix on the semiconductor substrate. FIG. 17 shows the MTJ memory cells arranged in n rows by m columns (where n, m is a natural number). Herein, n write word lines WWL1 to WWLn, n read word lines RWL1 to RWLn, and m bit lines BL1 to BLm are provided for the n×m MTJ memory cells.
In the data read operation, one of the read word lines RWL1 to RWLn is selectively activated, so that the memory cells on the selected memory cell row (hereinafter, sometimes simply referred to as “selected row”) are electrically coupled between the bit lines BL1 to BLm and the ground voltage VSS, respectively. As a result, the voltage on each bit line BL1 to BLm changes according to the storage data level in a corresponding memory cell.
Thus, the storage data level of the selected memory cell can be read by comparing the voltage on the bit line of the selected memory cell column (hereinafter, sometimes simply referred to as “selected column”) with a prescribed reference voltage using a sense amplifier or the like.
A dummy memory cell is generally used to produce such a reference voltage. For example, a dummy resistance having an electric resistance value Rd corresponding to an intermediate value of the electric resistance values R1 and R0 can be used as a dummy memory cell for use in the data read operation from the MTJ memory cell. The electric resistance values R1 and R0 respectively correspond to the electric resistance values of the MTJ memory cell storing the data “1 (H level)” and “0 (L level)”. The reference voltage can be produced by supplying the same sense current Is as that of the MTJ memory cell to the dummy resistance.
However, the data read operation requires the operation of charging and discharging a data line such as bit line to which a tunnel magnetic resistive element TMR having a relatively high electric resistance value is connected, thereby possibly making it difficult to increase the speed of the data read operation.
As described in the aforementioned technical documents, as a bias voltage applied to both ends of the magnetic tunnel junction, i.e., both ends of the tunnel magnetic resistive element TMR, is increased, a change in electric resistance value, ΔR, is reduced that corresponds to the relative relation of the magnetization direction between the fixed magnetic layer FL and the free magnetic layer VL, i.e., that corresponds to the storage data level. Therefore, as the voltage applied to both ends of the MTJ memory cell is increased in the data read operation, the voltage on the bit line does not noticeably change corresponding to the storage data level. This may possibly hinder the speed and stability of the data read operation.
Moreover, accuracy of the reference voltage is significantly affected by the electric resistance value of the dummy resistance in the dummy memory cell. Therefore, it is difficult to accurately set the reference voltage according to manufacturing variation.